Erivelto Luís de Souza, Universidade Federal de São João Del Rei – DTECH, Brazil

A novel architecture for decimating finite impulse response (FIR) filters has been introduced, demonstrating significant improvements in both efficiency and resource utilization. This state-of-the-art design employs a series of accumulators, each dedicated to accumulating a partial sum based on a distinct set of D filter coefficients, where D is defined as the decimation factor. In this innovative filtering architecture, the accumulated result from each individual accumulator is sequentially passed to the next accumulator for each group of D input samples. This process continues for all accumulators, with the exception of the last one, which is responsible for producing the final output of the filter. This cascading mechanism ensures that all contributions to the output are effectively integrated while minimizing redundancy. What sets this architecture apart is its inherently favorable characteristics compared to the widely adopted polyphase architecture. Most notably, it is expected to require significantly less physical area on chip while maintaining similar levels of dynamic power consumption. The reduced area requirement not only implies a potential reduction in manufacturing costs but also hints at enhanced integration capabilities within larger systems. Adopting this new architecture could result in substantial advancements in filter performance, making it a compelling option for engineers and developers working on advanced signal processing applications. By prioritizing efficiency and effectiveness, this architecture positions itself as a crucial tool in the evolution of FIR filter design.

APA:
De Souza, E. L. (2024). An Effective and Innovative FIR Filter Design that Leverages Linked Accumulators for Optimal Performance and Efficiency. Journal of Science and Engineering Management, 5(1), 21-32. https://doi.org/10.33832/jsem.2024.5.1.03