Advancement Through Research
Miniaturization of the dimensions of Metal Oxide Semiconductor field effect (MOSFET) transistors is very requisite nowadays for the enhanced enactment and integrated circuit compactness but this step of scaling arises to complications such as increased gate resistance and high leakage current. The utilization of integrated circuits in high-performance electronic gadgets is increasing day by day. As more and more complex functions are required in various fields like data/image processing and wired/wireless communication, the need to incorporate these functions in a compact package is also increasing. The reduction of channel length and other reduced parameters blemishes the device performance. The initial design can be designed and virtually fabricated in Computer-aided design (CAD) tool and the complexities of the design can be analysed at the early stage before the actual fabrication is done in fabrication laboratories. The scaling down of device dimensions results in a drastic increase in the sub-threshold leakage current of the device. There are various ways to reduce the leakage current of the device by increasing the work-function of the gate, variation of poly doping; halo doping and threshold implant concentration to reduce the leakage current of the device. To diminish these problems in Nano-scale transistors; there is massive interest in the variation of transistor's gate work-function. The experimental observations show that the devices with high gate work-function material have low leakage current as compared to low gate work-function devices. In this paper, 45nm P-MOSFET is virtually fabricated in ATHENA and simulated in ATLAS SILVACO. The work-function of the gate of PMOS is varied from 5.05eV to 5.32eV to estimate the leakage current of the device. The simulation result shows that the 9.35 nA/µm is achieved at gate work-function of 5.25eV.
PMOS, Athena, Atlas, Silvaco, CAD
